A number of memory devices, such as flash memory devices, use analog memory cells to store data. Each memory cell stores an analog value, also referred to as a storage value, such as an electrical charge or voltage. The storage value represents the information stored in the cell. In flash memory devices, for example, each analog memory cell typically stores a certain voltage. The range of possible analog values for each cell is typically divided into threshold regions, with each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired one or more bits.
The analog values stored in memory cells are often distorted. The distortions are typically due to, for example, back pattern dependency (BPD), noise and intercell interference (ICI). For a more detailed discussion of distortion in flash memory devices, see, for example, J. D. Lee et al., “Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation,” IEEE Electron Device Letters, 264-266 (May 2002) or Ki-Tae Park, et al., “A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories,” IEEE J. of Solid State Circuits, Vol. 43, No. 4, 919-928, (April 2008), each incorporated by reference herein.
A number of techniques have been proposed or suggested for mitigating the effect of ICI by reducing the capacitive coupling between cells. While there are available methods to reduce the effect of ICI, it is important that such ICI mitigation techniques do not unnecessarily impair the write-read speeds for flash controllers. Thus, many effective signal processing and decoding techniques are avoided that would introduce significant inherent processing delays. Foregoing such complex signal processing techniques, however, reduces the ability of a flash controller to maintain sufficient decoding accuracy as flash device geometries scale down.
It has been found that errors for neighboring bits in the pages of flash memory devices are correlated. A need therefore exists for detection and decoding techniques to combat errors that do not unnecessarily impair the read speeds for flash controllers. A further need exists for detection and decoding techniques that account for such error correlations.